The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device which is capable of improving a complexity of an etching process for forming a gate and preventing undesirable oxidation of a metal layer forming the gate.
In order to solve the problem of resistance generated as an effective area of a gate is decreased with high integration of a semiconductor device, tungsten (W) with superior thermal stability and filling characteristic is used as a gate material. However, when the tungsten is used as the gate material, an undesirable oxidation occurs in an exposed portion of the tungsten during the gate forming process. Accordingly, there has been suggested a method of forming a capping nitride layer on a side wall of the gate for preventing the undesirable oxidation from occurring in the exposed portion of the tungsten.
However, the conventional gate forming process including the process of forming the capping nitride layer for preventing the undesirable oxidation from occurring in the exposed portion of the tungsten is complex in an aspect of a process and may cause an undesirable problem due to localized generation of heat.
Specifically, the conventional method for manufacturing a semiconductor device including the formation of the capping nitride layer will be described with reference to FIGS. 1A through 1D.
Referring to FIG. 1A, a gate insulation layer 104 is formed over a semiconductor substrate 100 formed with an isolation layer 102 for defining an active region and a groove H for forming a recess gate and a polysilicon layer 106 is formed over the gate insulation layer 104 to fill the groove H. Over the polysilicon layer 106, a barrier layer 108, a tungsten layer 110, a hard mask layer 112, an amorphous carbon layer 114, an arc layer 116, and a mask pattern 118 made of photoresist and exposing an area for a gate to be formed are sequentially formed.
Referring to FIG. 1B, the arc layer (not shown), the amorphous layer (not shown) and the hard mask layer 112 are etched using the mask pattern (not shown) as an etching mask and then the mask pattern, the arc layer and the amorphous layer are removed. Then, the tungsten layer 110, the barrier layer 108 and some thickness of a surface of the polysilicon layer 106 are etched using the etched hard mask layer 112 as an etching mask.
Referring to FIG. 1C, a capping nitride layer 120 is formed over the etched polysilicon layer 106, barrier layer 108, tungsten layer 110 and hard mask layer 112.
Referring to FIG. 1D, the capping nitride layer 120, the polysilicon layer 106 some thickness of which is etched and the gate insulation layer 104 is etched to complete the formation of the gate.
As described above, the conventional gate forming method includes a first etching process in which the tungsten layer 110, the barrier layer 108 and some thickness of the polysilicon layer 106 are etched and a second etching process in which the capping nitride layer 120 and the rest portion of the firstly etched polysilicon layer 106 are etched. Therefore, the conventional gate forming process including the process of forming the capping nitride layer 120 is complex in an aspect of the process and is also hard to realize the process.
Further, heat of more than 700° C. is applied to a semiconductor substrate during the process of forming the capping nitride layer 120 and a gate leaning occurs consequently due to a difference of thermal expansion coefficient between various layers forming the gate.
In addition, since even the thickness of the capping nitride layer is also included in the critical dimension (CD) of the gate, a CD of the tungsten layer 110 is therefore decreased which leads to increase in a resistance of the gate.